Efficient Approximate Adder Architecture for Error Tolerant Applications with use of new logic values

--------------------------------------------------------------ABSTRACT------------------------------------------------------Ultra-high energy efficiency is required for all the battery operated devices due to increased functionality on the single chip. In conventional digital VLSI design, it is assumed that a circuit/system should function perfectly to provide accurate results.There are many applications which can tolerate small amount of error in their processing e.g. image/video processing, commonly called error tolerant applications.For many digital systems, the data already contained errors. The proposed adder can be efficiently utilized in the image video processing applications. In order to evaluate the efficacy of the proposed adder, proposed and existing adder architecture is implemented on MATLAB to evaluate error metrics and Tanner to evaluate design metrics. Simulation results shows that proposed adder significantly reduces power, area and delay at small loss in accuracy. Key Word:VLSI, MATLAB, Image processing, Adder,Highspeed integrated circuits -------------------------------------------------------------------------------------------------------------------------------------Date of Submission: 17 July 2015 Date of Accepted: 05 August 2015 --------------------------------------------------------------------------------------------------------------------------------------